Vitor Oliveira
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Executive Summary
Vitor Oliveira is a highly skilled professional with 16.2 years of experience in RTL design, Verilog, ASIC, TCL, static timing analysis, EDA, Pcie, SOC, logic synthesis, systemverilog, formal verification, functional verification, low power design, and FPGA prototyping. He is based in Porto, Portugal. Vitor is focused on architecture definition to address critical design challenges in digital controllers. He has expertise in addressing functional safety requirements at IP level and has experience with multiple protocols such as PCIe, MIPI DigRF, UniPro, and CSI. Vitor has worked at Synopsys Inc in various roles, including Manager R&D, Senior R&D Engineer
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Synopsys Inc
Research and Development Manager&Asic Digital Design Engr, Staff&Senior R&d Engineer&Asic Digital Design Engr, Staff
Research and Development Manager
Asic Digital Design Engr, Staff
Senior R&d Engineer
Asic Digital Design Engr, Staff
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