Vinav Patel
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Executive Summary
Vinav Patel is a highly skilled physical design engineer with 9.7 years of experience. He has expertise in verilog, asic, soc, and vlsi. Based in India, Vinav has successfully handled 16nm and 5nm block level physical design for networking and mobile processor chips. He has successfully tapeouts in 16nm and 1in 28nm, as well as tape-outs in 16nm and 1in 28nm. Vinav is familiar with industry standard tools and has completed training for "ASIC Physical Design" from eInfochips Training & Research Center.
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Current Workspace
Eximius Design
Senior Physical Design Engineer
Senior Physical Design Engineer
Professional Background
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