Vaibhav Garg is a problem solver with 7.4 years of experience in analog circuits, microprocessors, eagle, pspice, and pcb design. He has worked on Serdes PHYs for 5 years, specializing in RTL design, mixed signal modeling, and implementation. Vaibhav has expertise in frontend flows, creating constraints/environments for various PHY/subsystem/testchip projects. He is currently developing and supporting RTL and timing constraints for PCIe Gen6 PHY products and testchips. Vaibhav is dedicated to continuous innovation and is dedicated to being the same as he started his professional journey.

asic digital design engineer at synopsys&ASIC Digital Design Engineer II&ASIC Digital Design Engineer Senior&ASIC Digital Design Engineer II&ASIC Digital Design Engineer I
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