Pradeep Puppala
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Executive Summary
Pradeep Puppala is a highly skilled professional with 10.4 years of experience in Verilog, VLSI, Perl, Modelsim, and C. He holds a MSEE degree from the University of Texas at Dallas and is based in the United States. Pradeep has expertise in IC Design, Circuit Design, and Verification. He has hands-on experience in CMOS custom circuit design, dynamic CMOS circuit design, and low power methods. Pradeep has hands-on experience with ASIC Design & SRAM design, Cadence, Verification, DRC, LVS, Linux platform, and writing custom DRC rules and making custom scripts for CAD automation.
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Current Workspace
Apple
memory design engineer at apple
memory design engineer at apple
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