
Nishant Pathak is a B.Tech graduate in Electronics and communication with 8.3 years of work experience. He completed an M.tech in VLSI Design and completed an internship program at ST Microelectronics. Nishant has a strong background in PnR flow and has developed skills in static timing analysis, power intergrity, power analysis, signal integrity, and signoff closures. He has worked as a Senior Physical Design Engineer at Mirafra Technologies and Mindlance Technologies, as well as a Physical Design Engineer at Cientra and STMicroelectronics.

senior physical design engineer at mirafra technologies
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